Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a voltage controlled oscillator (VCO). In a single loop PLL, an output signal from a VCO is coupled to a programmable frequency divider which divides by a selected number to provide a frequency divided signal. The frequency divided signal is applied to a phase detector which compares the frequency divided signal to a reference signal from another fixed frequency oscillator. The reference signal is often selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal results in an output from the phase detector that is converted to a charge by the charge pump and coupled through a loop filter to create a correction signal. The correction signal is then applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized.
At radio frequencies (RF), frequency division becomes more difficult, and the result is that higher frequency performance is achieved at the expense of higher power consumption. In applications such as portable communication systems, higher power consumption decreases the talk time and the standby time available before subsequent battery recharging is necessary.
A way to lower the frequency performance requirement of the frequency divider is to distribute the frequency division process. A distributed frequency divider system would have a first frequency divider working at the RF frequency and a second frequency divider operating at the lower, divided frequency. For example, if the total frequency division required, N.sub.T is 189, the frequency division could be accomplished by dividing the RF signal first by a factor of 7, and then dividing the resultant signal by a factor of 27. The total frequency division of the output divided signal is then: EQU N.sub.T =(first division factor)*(second division factor)=(7)*(27)=189
By distributing the frequency division, only the first division process has to operate at the RF input frequency. A power savings would result by the relaxed frequency performance requirement of the second frequency divider.
The RF signal generated by the synthesizer is related to the overall divide number, N.sub.T, of the divider system. In order to change the frequency of the RF signal that is generated, the synthesizer must be programmable. This programmability is obtained in part by making the first and second dividers of the divider system programmable.
The basic structure of a conventional dual modulus frequency divider system suitable for use in a radiotelephone is shown in the block diagram of FIG. 1. A conventional dual modulus frequency divider system 150 utilizes a programmable divider 108 with a divider system input 100. The divided signal appearing at the programmable divider output 114 is directed to a first counter 110 and a second counter 112. The first counter 110 has a first program instruction input 106 to set the first counter 110 to a first counter value of "A". The second counter 112 has a second program instruction input 104 to set the second counter 112 to a second counter value of "N". The first counter 110 provides a divide (modulus) control 116 to the programmable divider 108 in order to set the divide value of the programmable divider 108. The second counter 112 is configured to have a divider system output 102. The first, high frequency division function of the overall distributed frequency division process is accomplished with the programmable divider 108. The second, lower frequency division function of the overall distributed frequency division process is accomplished by utilizing the first counter 110 and the second counter 112.
The programmable divider 108 is configured to have two programmable frequency division values (dual modulus). The first divide value is P+1, and the second divide value is P, where P is a predetermined value. The first counter 110 receives a first program instruction at the first program instruction input 106, and the second counter 112 receives a second program instruction at the second program instruction input 104. With the programming of the programmable divider variable, P, along with the programming of the first counter 110 and the second counter 112, the programming of the overall required divide ratio, N.sub.T, is accomplished.
The modulus control 116 sets the programmable divider 108 to the first divide value, P+1. The programmable divider 108 then divides the RF input signal appearing at the divider system input 100 by the first divide value, P+1. The first counter 110 counts the periods of the divided signal appearing at the programmable divider output 114. When the first counter 110 has counted A periods of the divided signal appearing at the programmable divider output 114, the first counter 110 uses the modulus control 116 to set the first divider 108 to its second divide value, P. The programmable divider 108 then divides the RF input signal appearing at the divider system input 100 by the second divide value, P, and the second counter 112 counts the periods of the divided signal appearing at the programmable divider output 114. When the second counter 112 has counted N-A additional periods of the divided signal appearing at the programmable divider output 114, the overall divide value, N.sub.T, has been achieved. The final output divided signal is produced at the divider system output 102. The total divide ratio, N.sub.T, is then defined by: EQU N.sub.T =PN+A
The second counter 112 is the master counter. When the second counter 112 fully decrements to a terminal value, such as 000, everything in the conventional dual modulus frequency divider system 150 is re-programmed. A single period of the output divided signal appearing at the divider system output 102 represents a single programming cycle. Beyond the initial programming of the first counter 110 to a count value of A and the second counter to a count value of N, no further programming is performed during a single programming cycle.
FIG. 2 is an example of the waveforms which would result when the overall divide ratio, N.sub.T, is set to 17, the first counter 110 is set to a count value of A=3, the second counter 112 is set to a count value of N=7, and P=2. At time 212, the first counter 110 and the second counter 112 are programmed to their A and N values, respectively. Also at time 212, the first counter 110 directs the modulus control signal 208 to the programmable divider 108. The programmable divider 108 then divides the RF input signal 200 by a factor of P+1=3, and the first counter 110 counts A=3 periods of the divided signal 202. The first counter signal 204 represents the decrementing value of the first counter 110. The second counter 112 also begins to decrement its value, although as long as the first counter 110 is still decrementing its value, the second counter 112 does not contribute to the division process. The second counter signal 206 represents the decrementing value of the second counter 112. After the first counter 110 has fully decremented at time 214, the modulus control signal 208 sets the programmable divider 108 to a divide value of P=2. The second counter 112 then counts N-A=4 additional periods of the divided signal 202 and produces the output divided signal 210 at the divider system output 102. When the second counter 112 has fully decremented at time 216, everything in the divider system is re-programmed.
A single period of the output divided signal 210 represents a single programming cycle. Beyond the initial programming of the first counter 110 to a count value of A and the second counter 112 to a count value of N, no further programming is performed during a single programming cycle.
There are several drawbacks associated with the conventional dual modulus frequency divider system. The first drawback is that the first counter 110 and the second counter 112 are always active, resulting in unnecessary power consumption. For example, when the first counter 110 is counting periods of the divided signal 202, the second counter 112 is still active and decrementing its value. The second drawback is that the final output divided signal 210 at the divider system output 102 has a duty cycle of much less that 50%. The resultant output divided signal 210 thus increases the bandwidth requirement of the circuitry that must further process the output divided signal 210. The third drawback is that the need for two separate counters increases the size and power consumption of the overall divider system. In portable communication systems, it is desirable to minimize size for ease of use and handling and to reduce manufacturing costs. The fourth drawback is that the A count value of the first counter 110 must always be less than the N count value of the second counter 112. If A was greater than N, then the second counter 112 would fully decrement and the system would be reset before the first counter 110 has finished decrementing.
In one known reference of a previous application, the prior art discloses a dual modulus programmable frequency divider that utilizes a pre-loadable binary ripple counter. The device pre-loads a count value, N1, into a pre-loadable binary counter but also pre-loads a compare value, N2, into a comparator. A prescaler divides the input signal by a first divide value, and the pre-loadable counter begins to count periods of the first divided signal produced by the prescaler. When the comparator detects the compare value, the prescaler is set to a second divide value, and the pre-loadable counter counts a remaining number of periods of the second divided signal.
Since the pre-loadable counter and the comparator are only loaded once during a complete frequency division period, this results in the limitation that N1 must be less than N2. This limitation can result in a final divided signal duty cycle that is not close to 50%. The limitation also can result in an increase in the number of flip-flops that are needed to make up the pre-loadable counter. Another drawback is that by using the arrangement of a pre-loadable counter and a comparator, the frequency performance of the device is limited because of the fact that the low current ripple counter places the constraint that all of the bits in the device must settle before the comparison function occurs. Also, the comparator utilizes combinatorial logic which further limits the frequency performance of the device. The comparator and the extra logic circuitry needed to link the comparator to the device also increases the overall size of the device.
In another known reference of a previous application, the prior art discloses a dual modulus programmable frequency divider that utilizes a single programmable counter which sequentially loads first an A count value and then a B count value. The device loads the A count value and the modulus control sets the prescaler to the first divide value. Once the counter reaches its final value, the modulus control sets the prescaler to the second divide value and the device loads the B count value. In this prior art approach, the modulus control signal is also the final output divided signal.
There are two significant drawbacks to this approach. First, since the output divided signal is also the modulus control signal, the A or B values cannot be programmed to equal zero. The capability to program either the A or B count value to equal zero is highly desirable for many applications for which the device would be used, and thus the inability to program the A or B count value to equal zero severely limits the system. Second, the critical path in terms of time delay in the device is from the prescaler output, to the binary counter output, to the selection flip-flop output, and finally through the selection of the A or B count value and the loading of the selected value into the binary counter. This time delay reduces the maximum speed and increases the power dissipation of the device. Circumventing the critical path in terms of time delay would therefore increase the speed of a single counter dual modulus system and also significantly reduce the power consumption.
Accordingly, there is a need for a dual modulus programmable frequency divider system that utilizes only one counter that is programmed twice during a single period of a final output divided signal. The single counter dual modulus frequency divider system must have the capability for the A and B count value to be programmed to zero. There is also a need to circumvent the critical timing path in single counter dual modulus frequency divider systems to both increase frequency performance and reduce power dissipation. In addition, there is a further need that the dual modulus programmable frequency divider system not contain a comparator circuit and the associated additional logic circuitry needed for the comparator interface. The result would be a power consumption and area savings, an increase in frequency performance, a removal of the constraint that A must be less than N, and a removal of the constraint that A and N must be greater than zero. An output divided signal that has a duty cycle close to 50% would also result.